The present invention relates to the field of digital circuits which share a common memory in general and to Lockstep arrangements in particular.
Lockstep arrangements have application in areas that demand highly reliable operation from data processing systems, which term is used here to include digital (also referred to as logic circuits) such as processor circuits. The term xe2x80x9cLockstepxe2x80x9d is used here to indicate a system where two, more or less identical digital circuits are run xe2x80x98in parallelxe2x80x99 and their operation monitored (eg in order to increase reliability and to detect faulty operation). If the behaviour of one of the circuits diverges from that of the other then a fault has occurred that can be detected so allowing remedial action to be taken.
Lockstep is normally applied to circuits that are synchronised to a clock signal. Hence xe2x80x9cin stepxe2x80x9d is used here to indicate, in synchronous circuits, events occurring within the same cycle of the clock signal.
By xe2x80x98run in parallelxe2x80x99 is meant that each circuit receives the same inputs in step and processes those inputs in step in order to generate identical outputs, also in step. In particular, the behaviour of the two digital circuits is the same every clock cycle after the assertion and de-assertion of reset, both for power up resets and for resets which stop and restart processing operation.
A Lockstep arrangement embodies Lockstep logic whose function is to keep the two digital circuits in step (or in synchronisation) and to detect any discrepancy in their behaviour, for example by comparing their outputs. If a fault is detected both circuits could be reset and a different pair of circuits, kept in reserve, initiated to take over the operation from the faulty circuits.
In the prior art, Lockstep arrangements have been applied to pairs of digital circuits, ie processor circuits, receiving identical inputs. In the Lockstep arrangements of the prior art, unless a fault occurs, in every clock cycle there is no difference in the behaviour of the devices of the two digital circuits. In every clock cycle, unless a fault occurs, the responses of the devices of the two digital circuits to every signal combination at their inputs is the same and the values at all output pins (including bidirectional pins) of the devices of the two digital circuits are the same.
In order to avoid the expense of a separate memory array for each circuit, the two digital circuits share a common memory. However whereas one circuit is able to read from and write to the common memory, the other is only able to read from it. Special circuitry is required to implement the interface to the common memory, conventionally in the form of a buffer on the read-only side. In conventional Lockstep arrangements this special circuitry is typically implemented by using fast ASIC circuitry, however these tend to be expensive and may be difficult to source.
By using the present invention it is possible to implement a Lockstep arrangement using standard commercially available components, for example, commercially available bridge devices.
The present invention provides a data processing system comprising a common memory, a first and second data processor circuit, each for executing the same sequence of operational steps and each connected to the common memory, an isolating device connected between the first data processor circuit and the common memory for restricting access to the common memory, in which the first data processor circuit is arranged to execute each operational step a set time period later than the second data processor circuit.